EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 198
![IC ACCLAIM MCU 256KB 144-BGA](/photos/12/15/121558/269-144-bga_sml.jpg)
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (3Mb)
PS019215-0910
Bit
Position Value
4
EPS
3
PEN
[2:0]
CHAR
0
1
0
1
000–111
Table 103. UART Character Parameter Definition
CHAR[2:0] Character Length (Tx/Rx Data Bits)
Description
Even Parity Select.
Use odd parity for transmit and receive. The total number of 1 bits in the transmit
data plus parity bit is odd. Used as SPACE bit in Multidrop Mode. See
page 189 for parity select definitions. Note: Receive Parity is set to SPACE in
multidrop mode.
Use even parity for transmit and receive. The total number of 1 bits in the transmit
data plus parity bit is even. Used as MARK bit in Multidrop Mode. See
page 189 for parity select definitions.
Parity bit transmit and receive is disabled.
Parity bit transmit and receive is enabled. For transmit, a parity bit is generated and
transmitted with every data character. For receive, the parity is checked for every
incoming data character. In Multidrop Mode, receive parity is checked for space
parity.
UART Character Parameter Selection.
See
000
001
010
100
101
011
110
111
Table 103
on page 189 for a description of the values.
5
6
7
8
5
6
7
8
Universal Asynchronous Receiver/Transmitter
Stop Bits (Tx Stop Bits)
Product Specification
1
1
1
1
2
2
2
2
eZ80F91 MCU
Table 104
Table 104
on
on
189
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