PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 107

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.2
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and contained in three separate 8-bit registers.
The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register are performed
through the PCLATH register. The upper byte is called
PCU. This register contains the PC<20:16> bits; it is also
not directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred to
the program counter by any operation that writes PCL.
Similarly, the upper two bytes of the program counter are
transferred to PCLATH and PCLATU by an operation
that reads PCL. This is useful for computed offsets to the
PC (see
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit (LSb) of PCL is
fixed to a value of ‘ 0 ’. The PC increments by two to
address sequential instructions in the program memory.
The CALL , RCALL , GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
6.1.3
The return address stack enables execution of any
combination of up to 31 program calls and interrupts.
The PC is pushed onto the stack when a CALL or
RCALL instruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack on
a RETURN , RETLW or a RETFIE instruction. The value
is also pulled off the stack on ADDULNK and SUBULNK
instructions if the extended instruction set is enabled.
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
FIGURE 6-3:
 2011 Microchip Technology Inc.
Section 6.1.5.1 “Computed GOTO”
PROGRAM COUNTER
RETURN ADDRESS STACK
Top-of-Stack Registers
TOSU
00h
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
TOSH
1Ah
TOSL
34h
Top-of-Stack
).
Return Address Stack<20:0>
Preliminary
001A34h
000D58h
PIC18F66K80 FAMILY
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack (TOS) Special Function Registers. Data
can also be pushed to, or popped from the stack, using
these registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL ). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘ 00000 ’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘ 00000 ’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.3.1
Only the top of the return address stack is readable and
writable. A set of three registers, TOSU:TOSH:TOSL,
holds the contents of the stack location pointed to by
the STKPTR register
implement a software stack, if necessary. After a CALL ,
RCALL or interrupt (or ADDULNK and SUBULNK instruc-
tions, if the extended instruction set is enabled), the
software can read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the
TOSU:TOSH:TOSL and do a return.
While accessing the stack, users must disable the
global interrupt enable bits to prevent inadvertent stack
corruption.
11111
11110
11101
00011
00010
00001
00000
software
Top-of-Stack Access
can
(Figure
return
STKPTR<4:0>
Stack Pointer
00010
6-3). This allows users to
these
DS39977C-page 107
values
to