IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 10

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Contents
Chapter 8. Testbench
Appendix A. Using PCI Constraint File Tcl Scripts
x
PCI Compiler User Guide
PCI Host-Bridge Operation ................................................................................................................ 7–45
Altera-Provided PCI Bus Arbiter ...................................................................................................... 7–45
Interrupts .............................................................................................................................................. 7–46
Control & Status Registers ................................................................................................................. 7–47
General Description ............................................................................................................................... 8–1
Features ................................................................................................................................................... 8–2
PCI Testbench Files ............................................................................................................................... 8–3
Testbench Specifications ....................................................................................................................... 8–4
Simulation Flow ................................................................................................................................... 8–15
Introduction ........................................................................................................................................... A–1
PCI Constraint Files .............................................................................................................................. A–1
Simultaneous Switching Noise (SSN) Considerations .................................................................... A–2
Additional Options ............................................................................................................................... A–3
PCI Interrupt Status Register ........................................................................................................ 7–49
PCI Interrupt Enable Register ...................................................................................................... 7–51
PCI Mailbox Register Access ........................................................................................................ 7–52
Avalon-to-PCI Address Translation Table ................................................................................. 7–53
Read-Only Configuration Registers ............................................................................................ 7–54
Avalon-MM Interrupt Status Register ........................................................................................ 7–56
Avalon-MM Interrupt Enable Register ....................................................................................... 7–60
Avalon Mailbox Register Access .................................................................................................. 7–60
Master Transactor (mstr_tranx) ...................................................................................................... 8–5
Target Transactor (trgt_tranx) ...................................................................................................... 8–12
Bus Monitor (monitor) ................................................................................................................... 8–13
Arbiter (arbiter) .............................................................................................................................. 8–14
Pull Up (pull_up) ........................................................................................................................... 8–14
Ordering PCI-to-Avalon Operations ...................................................................................... 7–42
Generation of PCI Interrupts ................................................................................................... 7–46
Reception of PCI Interrupts ..................................................................................................... 7–46
Generation of Avalon-MM Interrupts ................................................................................... 7–47
PROCEDURES and TASKS Sections ........................................................................................ 8–5
INITIALIZATION Section ......................................................................................................... 8–6
USER COMMANDS Section ..................................................................................................... 8–7
cfg_rd ............................................................................................................................................ 8–7
cfg_wr ........................................................................................................................................... 8–8
mem_wr_32 .................................................................................................................................. 8–8
mem_rd_32 .................................................................................................................................. 8–9
mem_wr_64 ................................................................................................................................ 8–10
mem_rd_64 ................................................................................................................................ 8–11
io_wr ........................................................................................................................................... 8–11
io_rd ............................................................................................................................................ 8–11
FILE IO section .......................................................................................................................... 8–13
PROCEDURES and TASKS sections ...................................................................................... 8–13
PCI Compiler Version 10.1
Altera Corporation