IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 42

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI MegaCore Function Design Walkthrough
1–8
PCI Compiler User Guide
<variation name>.v or .vhd
<variation name>_bb.v
<variation name>.bsf
<variation name>.qip
<variation name>_syn.v
<variation name>.ppf
<variation name>.vo or .vho
pci_constraints_for_<variation
name>.tcl
<variation name>_nativelink.tcl
<variation name>.html
Table 1–1. IP Toolbench-Generated Files
Extension
To generate your MegaCore function, follow these steps:
1.
Click Step 3: Generate in IP Toolbench. A summary of files
generated to your project directory is displayed.
Table 1–1
your project directory. The names and types of files specified in the
IP Toolbench report vary based on whether you created your design
with VHDL or Verilog HDL.
A MegaCore function variation file that defines a VHDL or Verilog HDL
top-level description of the custom MegaCore function. Instantiate the
entity defined by this file inside of your design. Include this file when
compiling your design in the Quartus II software.
A Verilog HDL black box file for the MegaCore function variation. Use this
file when using a third-party EDA tool to synthesize your design.
A Quartus II symbol file for the MegaCore function variation. You can use
this file in the Quartus II block diagram editor.
Contains Quartus II project information for your MegaCore function
variations.
A timing and resource estimation netlist for use in some third-party
synthesis tools. This file is generated when the option Generate netlist on
the EDA page is turned on.
This XML file describes the MegaCore pin attributes to the Quartus II Pin
Planner. MegaCore pin attributes include pin direction, location, I/O
standard assignments, and drive strength. If you launch IP Toolbench
outside of the Pin Planner application, you must explicitly load this file to
use Pin Planner.
A Verilog HDL or VHDL IP functional simulation model.
A tcl script for assigning timing constraints to the MegaCore function.
A tcl script for assigning NativeLink simulation testbench settings to the
Quartus project.
A MegaCore function report file.
PCI Compiler Version 10.1
describes the generated files and other files that may be in
Description
Altera Corporation
January 2011