IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 323

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
6:0
7
8
9
10
11
12
13
15:14 Reserved
19:16
23:20
31:24 Reserved
Table 7–23. General Configuration Parameters – Address 0x2C00
Bit
PCI_ADDRESS_WIDTH
Reserved
TARGET_ONLY
HOST_BRIDGE_MODE
PCI_BUS_64
COMMON_CLOCK_MODE
IMPL_PREF_PORT
IMPL_NONP_PORT
NUM_A2P_MAILBOX
NUM_P2A_MAILBOX
Name
Table 7–23
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Access
Mode
PCI Compiler Version 10.1
lists some basic configuration parameters of the bridge.
Indicates whether 32- or 64-bits of PCI addressing are kept
on the Avalon-to-PCI path. Unimplemented upper bits are
always forced to 0 in the address phase of a PCI bus
transaction.
Reserved
Indicates that you have selected the PCI Target-Only
Peripheral mode (refer to
Indicates that you have selected the PCI Host-Bridge Device
mode (refer to
Indicates that you have selected the 64-Bit PCI Bus option
(refer to
Indicates that you have selected the Shared PCI and Avalon
Clocks option (refer to
page
Indicates that the prefetchable Avalon-MM master port is
implemented.
Indicates that the non-prefetchable Avalon-MM master port
is implemented.
Reserved
Reflects the number of implemented Avalon-to-PCI mailbox
registers.
Reflects the number of PCI-to-Avalon mailbox registers.
Reserved
6–6).
“Value of Multiple Pending Reads” on page
“System Options-1” on page
“Value of Multiple Pending Reads” on
Description
“System Options-1” on page
Functional Description
6–1).
6–6).
6–1).
7–55