IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 66

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Variation File Parameters
2–8
PCI Compiler User Guide
VEND_ID
BAR0 (2)
BAR1 (2)
BAR2 (2)
BAR3 (2)
BAR4 (2)
BAR5 (2)
EXP_ROM_BAR
Table 2–1. PCI MegaCore Function Parameters (Part 2 of 5)
Name
Hexadecimal
Hexadecimal
Hexadecimal
Hexadecimal
Hexadecimal
Hexadecimal
Hexadecimal
String
Format
PCI Compiler Version 10.1
H"1172"
H"FFF00000"
H"FFF00000"
H"FFF00000"
H"FFF00000"
H"FFF00000"
H"FFF00000"
H"FF000000"
Default Value
Device vendor ID register. This parameter is
a 16-bit hexadecimal value that sets the
vendor ID register in the PCI configuration
space. The value for this parameter can be
the Altera vendor ID (1172 Hex) or any
other PCI SIG-assigned vendor ID number.
Base address register (BAR) zero. When
implementing a 64-bit base address register
that uses BAR0 and BAR1, BAR0 contains
the lower 32-bit address. For more
information, refer to
Registers (BARs)” on page
Base address register one. When
implementing a 64-bit base address register
that uses BAR0 and BAR1, BAR1 contains
the upper 32-bit address. When
implementing a 64-bit base address register
that uses BAR1 and BAR2, BAR1 contains
the lower 32-bit address. For more
information, refer to
Registers (BARs)” on page
Base address register two. When
implementing a 64-bit base address register
that uses BAR1 and BAR2, BAR2 contains
the upper 32-bit address. For more
information, refer to
Registers (BARs)” on page
Base address register three.
Base address register four.
Base address register five.
Expansion ROM. This value controls the
number of bits in the expansion ROM BAR
that are read/write and will be decoded
during a memory transaction.
Description
“PCI Base Address
“PCI Base Address
“PCI Base Address
Altera Corporation
2–2.
2–2.
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January 2011