IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 306

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–38
PCI Compiler User Guide
The Avalon-to-PCI address translation table has two configurations (refer
to
■
■
If Dynamic Translation Table is specified, translation table entries can be
modified, as needed, by the software at run time. If Fixed Translation
Table is specified, the translation table entries are fixed at compile time.
The dynamic Avalon-to-PCI address translation table has the following
properties:
■
■
■
Some applications can use a fixed Avalon-to-PCI address map. Because
Host Bridge applications program the BAR registers on the attached PCI
devices, they can control which PCI address ranges are used. If a large
enough range of the Avalon-MM address space can be set aside to map
all of the BARs in a system, then a single fixed Avalon-to-PCI map can be
used. Even in PCI Target-Only Peripheral mode or PCI Master/Target
Peripheral mode, many embedded applications will know enough about
the required PCI addressing to get by with a small number of fixed
Avalon-to-PCI translations.
Fixed address translations operate identically to the modifiable scheme
described above, except that the translation table effectively becomes a
read only memory (ROM). The same parameters control the size of the
now fixed translation table.
Ordering of Requests
The PCI-Avalon bridge handles the following types of requests:
■
■
■
“Avalon Configuration” on page
Dynamic
Fixed
The table can be written to via the control register access port
Entries must be set up before read or write requests are issued to the
corresponding Avalon-MM addresses
The table cannot be preinitialized upon reset
PMW—Posted memory write
DRR—Delayed read request
DWR—Delayed write request. DWRs are I/O or configuration write
operation requests. The PCI-Avalon bridge does not handle DWRs
as delayed writes. As a:
●
PCI master, I/O or configuration writes are generated from
posted Avalon-MM writes. If required to verify completion, you
must issue a subsequent read request to the same target.
PCI Compiler Version 10.1
6–16):
Altera Corporation
January 2011