IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 299

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 7–9. Avalon-to-PCI Block Diagram
Altera Corporation
January 2011
MegaCore
Function
PCI
Command
Controller
Arbiter/
Master
PCI
I/O and Cfg Requests
Avalon-to-PCI Write Requests
For write requests from the interconnect, the write request is pushed on
to the PCI bus as a configuration write, I/O write, or memory write.
When the Avalon-to-PCI command/write data buffer either has enough
data to complete the full burst or 8 data phases (32 bytes on a 32-bit PCI
bus or 64 bytes on a 64-bit bus) are exceeded, the PCI master controller
will issue the PCI write transaction.
The PCI write is issued to configuration, I/O, or memory space based on
the address translation table. Refer to
Translation” on page
For all PCI memory write commands, a linear incrementing burst order
is used.
Data
Read Cmd Buffer
Pending Read N
Control/Address
Pending Read 0
Control/Address
Control/Address
Pending Read
Data
Current Write
Bypassable
PCI Compiler Version 10.1
PCI Clock Domain
Addr
Addr
Wr
Wr
Rd
Wr
7–35.
Data Buffer
Command/
Resp Buffer N
Resp Buffer 0
Read Control
Resp Buffer
Resp Buffer
Avalon Clock Domain
“Avalon-to-PCI Address
Read/Write
Read
Addr
Functional Description
Interface
Control
Avalon
Translation
Logic
Addr
PCI Bus Access
Avalon Slave
Control
Control
Read
Data
Write
Addr
Data
7–31