IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 106

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–32
PCI Compiler User Guide
0
1
2
3
4
5
6
7
8
9
10
15..11
Table 3–16. Command Register Format
Data
Bit
io_ena
mem_ena
mstr_ena
Unused
mwi_ena
Unused
perr_ena
Unused
serr_ena
Unused
int_dis
Unused
Mnemonic
Read/write
Read/write
Read/write
–
Read/write
–
Read/write
–
Read/write
–
Read/write
–
Read/Write
Command Register
Command is a 16-bit read/write register that provides basic control over
the ability of the PCI function to respond to the PCI bus and/or access it.
Refer to
Table
PCI Compiler Version 10.1
I/O access enable. When high,
the PCI bus I/O accesses as a target.
Memory access enable. When high,
respond to the PCI bus memory accesses as a target.
Master enable. When high,
mastership of the PCI bus. Bit 2 is hardwired to
host bridge options are enabled through the wizard.
–
Memory write and invalidate enable. This bit controls whether the
master may generate a MWI command. Although the function
implements this bit, it is ignored. The local side must ensure that the
mwi_ena
the MWI command.
–
Parity error enable. When high,
report parity errors via the
–
System error enable. When high,
report address parity errors via the
a system error, the
–
Interrupt disable. A value of 1 disables the PCI MegaCore function
from asserting
disabled after the preexisting interrupt has been serviced.
–
3–16.
output is high before it requests a master transaction using
intan
perr_ena
on the PCI bus. However, the interrupt is only
perrn
mstr_ena
Definition
io_ena
bit must also be high.
perr_ena
serr_ena
serrn
output.
mem_ena
allows the function to request
lets the function respond to
output. However, to signal
enables the function to
allows the function to
lets the function
1
Altera Corporation
when PCI master
January 2011