IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 303

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
The transaction arbiter issues eligible commands in the following order:
1.
2.
3.
4.
Avalon-to-PCI Address Translation
Avalon-to-PCI address translation is done through a translation table.
Low order Avalon-MM address bits are passed to PCI unchanged; higher
order Avalon-MM address bits are used to index into the address
translation table. The value found in the table entry is used as the higher
order PCI address bits.
1
Head-of-line previously retried or disconnected read request that
was not the last command issued.
Previously disconnected or never issued eligible write request.
Not head-of-line previously retried or never issued read request. If
there are multiple not head-of-line retried or never issued reads, this
priority slot is given to each of them one at a time in a rotating
order, so that the head-of-line read request is issued at least once
every other command.
Head-of-line previously retried read request that was the last
command issued.
PCI Compiler Version 10.1
The head-of-line read command in the pending read queue
is the one that is issued first and its read data must be
returned before the data for all other reads is returned.
Because the interconnect is waiting for the head-of-line
command data to be returned first, it is given a special
priority level.
Figure 7–10
depicts this process.
Functional Description
7–35