IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 183

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
3.
1
4.
The pci_mt64 and pci_mt32 functions treat memory write and
memory write and invalidate in the same way. Any additional
requirements for the memory write and invalidate command must be
implemented by the local-side design.
The PCI function begins the PCI address phase. During the PCI
address phase, the local side must provide the byte enables for the
transaction on the l_cbeni bus. For burst transactions, byte
enables are used throughout the transaction. At the same time, the
PCI side turns on the driver for irdyn.
If the address of the transaction matches the memory range
specified in the base address register (BAR) of a PCI target, the PCI
target asserts devseln to claim the transaction. One or more data
phases follow next, depending on the type of write transaction.
You can change the byte enables for the successive data words
in burst transactions by turning on Allow Variable Byte Enable
During Burst Transactions option in the Advanced PCI
MegaCore Function Features page of the Parameterize - PCI
Compiler wizard. Refer to
Burst Transactions” on page 2–5
option.
PCI Compiler Version 10.1
“Allow Variable Byte Enables During
for more information about this
Functional Description
3–109