IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 100

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–26
PCI Compiler User Guide
Note to
(1)
Table 3–10. pci_mt64 & pci_mt32 Local Master Transaction Status Register (lm_tsr[9..0]) Bit
Definition
Bit Number
Some arbiters may initially assert gntn (in response to either the pci_mt64 or pci_mt32 function requesting
mastership of the PCI bus), but then deassert gntn (before the pci_mt64 or pci_mt32 have asserted framen) to
give mastership of the bus to a higher priority device. In systems where this situation may occur, the local side logic
should hold the address and command on the l_adi[63..0] and l_cbeni[7..0] buses until the adr_phase
bit is asserted (lm_tsr[2]) to ensure that the pci_mt64 or pci_mt32 function has assumed mastership of the
bus and that the current address and command bits have been transferred.
1
2
3
4
5
6
7
8
9
0
(1)
(1)
Table
(1)
3–10:
adr_phase
dat_phase
disc_wod
request
lat_exp
disc_wd
dat_xfr
trans64
Bit Name
grant
retry
Table 3–10
register outputs.
Request. This signal indicates that the
requesting mastership of the PCI bus (i.e., it is asserting its
request
parked on the
already asserted when the function requests mastership of the bus.
Grant. This signal is active after the
detected that
Address phase. This signal is active during a PCI address phase where
pci_mt64
Data phase. This signal is active while the
is in data transfer mode. The signal is active after the address phase and
remains active until the turn-around state begins.
Latency timer expired. This signal indicates that
terminated the master transaction because the latency timer counter expired.
Retry detected. This signal indicates that the
function terminated the master transaction because the target issued a retry.
Per the PCI specification, a transaction that ends in a retry must be retried at
a later time.
Disconnect without data detected. This signal indicates that the
pci_mt32
issued a disconnect without data.
Disconnect with data detected. This signal indicates that
pci_mt32
disconnect with data.
Data transfer. This signal indicates that a successful data transfer occurred on
the PCI side in the preceding clock cycle. This signal can be used by the local
side to keep track of how much data was actually transferred on the PCI side.
64-bit transaction. This signal indicates that the target claiming the transaction
asserted its
transactions, this signal is reserved.
PCI Compiler Version 10.1
shows definitions for the local master transaction status
bit is not asserted if the following is true: The PCI bus arbiter has
or
signal terminated the master transaction because the target
ack64n
terminated the master transaction because the target issued a
gntn
pci_mt64
pci_mt32
is asserted.
signal. Because
or
is the bus master.
pci_mt32
Description
pci_mt64
pci_mt32
pci_mt64
function and the
pci_mt64
pci_mt64
or
pci_mt64
does not request 64-bit
pci_mt32
or
pci_mt32
or
pci_mt32
pci_mt64
or
Altera Corporation
gntn
reqn
pci_mt32
or
pci_mt64
function has
pci_mt32
January 2011
signal is
signal). The
function is
function
or
or