IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 286

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Target Operation
7–18
PCI Compiler User Guide
PCI-to-Avalon non-prefetchable command already in
progress
Normal master initiated termination of single data
phase transaction
Table 7–4. Non-Prefetchable Write Operation
Termination Condition
To ensure the lowest possible latency, the PCI-Avalon bridge can handle
just one PCI-to-Avalon, non-prefetchable request at a time. A single
command register holds the command, address, and byte enables for
either the current read or the current write operation. If the register is still
busy with the previous operation, no additional read or write requests are
accepted and a retry is signaled on the PCI interface.
Non-Prefetchable Write Operations
The non-prefetchable bridge data path handles both the memory write
command and the memory write and invalidate command if they hit
either:
■
■
■
When PCI write requests are claimed from the PCI bus, they are passed
to Avalon-MM as write requests. Both PCI memory write and PCI
memory write and invalidate PCI bus commands are treated identically
inside the non-prefetchable PCI-Avalon bridge logic. The first data phase
worth of data is accepted from the PCI bus and written to the
PCI-to-Avalon write data register. A target disconnect is signaled as the
first data phase is accepted from the PCI bus.
The PCI-to-Avalon address translation circuit is used to compute the
appropriate Avalon-MM address. The non-prefetchable Avalon-MM
master port will then issue a single-cycle Avalon-MM write transaction to
transfer data.
Table 7–4
non-prefetchable PCI target write operations.
A non-prefetchable BAR.
A prefetchable BAR when the Single-Cycle Transfers Only target
performance profile is selected.
An I/O BAR.
shows all of the possible termination conditions for
PCI Compiler Version 10.1
The target controller retries the operation on the PCI
bus. Nothing is remembered about the retried PCI write
operation. When the PCI write operation is
subsequently re-issued, it is treated as a new
operation.
Data is accepted and written to the PCI-to-Avalon
non-prefetchable data register and then written to
Avalon.
Resulting Action
Altera Corporation
January 2011