IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 269

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional
Overview
Altera Corporation
January 2011
This chapter provides specification details for the PCI Compiler with
SOPC Builder flow, including:
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The PCI Compiler with SOPC Builder flow uses the PCI-Avalon
to connect the PCI bus to the on-chip system interconnect fabric, allowing
you to easily create simple or complex PCI systems that include one or
more of the SOPC Builder components.
Because the PCI Compiler with SOPC Builder flow uses a predefined
interconnect, system development is completely driven by the SOPC
Builder graphical user interface (GUI). For example, you specify bridge
and component parameterization options, and the PCI Compiler wizard
sets up the bridge’s structure, component features, and system-wide
interconnect.
To make a complete PCI-Avalon bridge, the PCI Compiler instantiates
the Altera pci_t32, pci_t64, pci_mt32, or pci_mt64 MegaCore
function as needed per user specifications.
The interconnect—which contains logic to manage system-wide
connectivity—connects all components that make up the user-specified
SOPC Builder system. For example, when the targeted Altera device is
operating in the PCI Master/Target Peripheral mode, the PCI-Avalon
bridge (via the interconnect) is managing the connectivity of multiple
master and slave components.
Functional Overview
Interface Signals
PCI Bus Commands
PCI Target Operation
PCI Master Operation
PCI Host-Bridge Operation
Altera-Provided PCI Bus Arbiter
Interrupts
Control & Status Registers
PCI Compiler Version 10.1
7. Functional Description
™
bridge
7–1