IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 70

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Variation File Parameters
2–12
PCI Compiler User Guide
8
9
10
11
12
Number
Table 2–2. Bit Definition of the ENABLE_BITS Parameter (Part 2 of 5)
Bit
CAP_LIST_ENA
CIS_PTR_ENA
INTERRUPT_ACK_ENA
Reserved
INTERNAL_ARBITER_ENA (1)
Bit Name
PCI Compiler Version 10.1
0
0
0
0
0
Default
Value
Capabilities list enable. This bit determines if the
capabilities list will be enabled in the configuration
space. When this bit is set to 1, it sets the
capabilities list bit (bit 4) of the status register and
sets the capabilities register to the value of
CAP_PTR.
CardBus CIS pointer enable. This bit enables the
CardBus CIS pointer register. When this bit is set
to 0, the function returns H"00000000" during a
configuration read to the CIS_PTR register.
Interrupt acknowledge enable. This bit enables
support for the interrupt-acknowledge command.
When set to 0, the function ignores the interrupt
acknowledge command. When set to 1, the
function responds to the interrupt acknowledge
command. The function treats the interrupt
acknowledge command as a regular target
memory read. The local side must implement the
necessary logic to respond to the interrupt
controller.
Reserved.
This bit allows reqn and gntn to be used in
internal arbiter logic without requiring external
device pins. If the PCI MegaCore function and a
PCI bus arbiter are implemented in the same
device, the reqn signal should feed internal logic
and gntn should be driven by internal logic
without using actual device pins. If this bit is set to
1, the tri-state buffer on the reqn signal is
removed, allowing an arbiter to be implemented
without using device pins for the reqn and gntn
signals.
Definition
Altera Corporation
January 2011