IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 260

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

System Options-2
6–10
PCI Compiler User Guide
The Shared PCI and Avalon Clocks option allows the PCI bus and
Avalon-MM interface to use a single clock, resulting in a simpler system
that uses fewer logic resources. Additionally, the resulting system’s
latency is lower than is possible with separate clocks. When you select
this option, the SOPC Builder generates a system with only one clock pin
driving the PCI-Avalon bridge. The clock pin name will not have the
PCI-Avalon bridge instance name, and should be connected to the PCI
clock source.
PCI Bus Arbiter
The PCI Bus Arbiter options are disabled if you select PCI Target-Only
Peripheral mode. If you select either PCI Master/Target Peripheral or
PCI Host-Bridge Device mode, you can define how the reqn and gntn
signals are routed. The default is to route the signals to external pins.
The following defines the PCI Bus Arbiter selections:
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■
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Arbiter External to Device—this is the most common option and is
also the default setting. Because the PCI bus arbitration is done
outside of the FPGA device, the Arbiter External to Device option is
common for all PCI add-on applications. Selecting this option routes
the reqn and gntn signals to pins.
User-Defined Arbiter Internal to Device—Selecting this option
allows you to connect the reqn and gntn signals of the PCI-Avalon
bridge to internal logic and not drive them to pins. This option
disables the tri-state buffer on the reqn signal.
Altera-Provided Arbiter Internal to Device—This option enables the
arbiter shipped with the PCI-Avalon bridge. Similar to the
User-Defined Arbiter Internal to Device option, this option disables
the tri-state buffer on reqn signal. Additionally, this option wires the
reqn and gntn signals to the provided arbiter as device #0, i.e., the
reqn and gntn signals are internally connected to ArbReq_n_i[0]
and ArbgGnt_n_o[0] respectively.
If you select this option, you need to specify the number of PCI
devices supported by the MegaCore function. The provided arbiter
can support up to eight PCI devices. The number of devices
supported includes the PCI-Avalon bridge; therefore, if you select
two devices, there will be one PCI device in addition to the
PCI-Avalon bridge device on the PCI bus.
PCI Compiler Version 10.1
Altera Corporation
January 2011