IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 338

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
8–8
PCI Compiler User Guide
cfg_wr
The cfg_wr command performs single-cycle PCI configuration write
transactions with the address, data, and byte enable provided in the
command arguments.
mem_wr_32
The mem_wr_32 command performs a memory write with the address
and data provided in the command arguments. This command can
perform a single-cycle or burst 32-bit memory write depending on the
number of DWORDs provided in the command argument.
■
■
Syntax:
Arguments:
Syntax:
Arguments:
The mem_wr_32 command performs a single-cycle 32-bit memory
write if the DWORD value is 1.
The mem_wr_32 command performs a burst-cycle 32-bit memory
write if the DWORD value is greater than 1. In a burst transaction, the
first data phase uses the data value provided in the command. The
subsequent data phases use values incremented sequentially by 1
from the data provided in the command argument.
PCI Compiler Version 10.1
cfg_wr(address, data, byte_enable)
address
data
byte_enable
mem_wr_32(address, data, dword)
address
data
dword
Transaction address. This value must be in
hexadecimal radix.
Data used for the first data phase. Subsequent
data phases use a value incremented sequentially
by 1. This value must be in hexadecimal radix.
The number of
transaction. A value of 1 indicates a single-cycle
memory write transaction. A value greater than one
indicates a burst transaction. This value must be an
integer.
Transaction address. This value must be in
hexadecimal radix.
Transaction data. The data must be in
hexadecimal radix.
Transaction byte enable. The byte enable
value must be in hexadecimal radix
DWORD
s written during the
Altera Corporation
January 2011