IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 348

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simultaneous Switching Noise (SSN) Considerations
Simultaneous
Switching Noise
(SSN)
Considerations
A–2
PCI Compiler User Guide
4.
5.
If you are upgrading from a previous version of PCI compiler, refer to
“Upgrading Assignments from a Previous Version of PCI Compiler” on
page A–6
PCI MegaCore functions implement a multiplexed high-width address
and data (ad) bus. Simultaneous switching noise (SSN) can occur if the
bus changes state from 0xFFFF_FFFF to 0x0000_0000, causing ground
bounce.
c
To reduce ground bounce, the PCI constraint files for MAX II devices
assign several programmable ground pins near the pins used for the PCI
ad bus. These pins must be physically connected to ground plane on your
board.
These programmable grounds are assigned in the QSF as follows:
set_location_assignment <pin location> -to <reserve pin name>
set_instance_assignment -name RESERVE_PIN "AS OUTPUT
DRIVING GROUND" -to <reserve pin name>
Source the constraint file by typing the following in the Quartus II
Tcl Console window:
source pci_constraints_for_<variation name>.tcl r
Add the PCI constraints to your project by typing the following
command in the Quartus II Tcl Console window:
add_pci_constraints r
Refer to
be used with add_pci_constraints command.
When you add the PCI constraints file in Step 5 above, the Quartus II
software generates a Synopsys Design Constraints (.sdc) file with the
file name format, <variation name>.sdc file. The Quartus II
TimeQuest timing analyzer uses the constraints specified in this file.
f
SSN can cause instability to your system. You can avoid
instability by assigning the pins for the address and data (ad)
bus farther away from the analog power supply pins (VCCA and
VCCA_PLL).
for more information.
PCI Compiler Version 10.1
“Additional Options” on page A–3
For more information on .sdc file or TimeQuest timing
analyzer, refer to Quartus II Help.
for the options that can
Altera Corporation
January 2011