IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 157

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–27. Disconnect in a Burst Read Transaction
Note to
(1)
Altera Corporation
January 2011
(1) l_adi[63..32]
(1) ad[63..32]
(1) cben[7..4]
This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
l_adro[31..0]
l_cmdo[3..0]
l_adi[31..0]
lt_tsr[11..0]
(1) ack64n
(1) req64n
cben[3..0]
lt_framen
(1) par64
ad[31..0]
devseln
lt_discn
lt_dxfrn
Figure
lt_ackn
framen
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
3–27:
2
000
Adr
6
3
Figure 3–27
transaction, and it applies to all PCI functions—excluding the 64-bit
extension signals as noted for pci_mt32 and pci_t32. During burst
target read transactions, lt_discn should be asserted with the last data
phase on the local side. The lt_rdyn signal is asserted during clock cycle
5 indicating that valid data will be available on the local side in clock cycle
6. Then, lt_discn is asserted in clock cycle 7 indicating the last data
phase to be completed on the local side.
Adr-PAR
4
Z
Z
PCI Compiler Version 10.1
Z
shows an example of a disconnect during a burst target read
5
BE0_H
BE0_L
6
381
D0_H
D0_L
7
D0_H
D1_H
D0_L
D1_L
8
D0-H-PAR
D0-L-PAR
BE1_L
BE1_H
D1_H
D1_L
Adr
6
9
781
D1-H-PAR
D1-L-PAR
10
Functional Description
11
381
12
000
13
3–83