IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 144
IPR-PCI/MT32
Manufacturer Part Number
IPR-PCI/MT32
Description
IP CORE Renewal Of IP-PCI/MT32
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 144 of 358
- Download datasheet (3Mb)
Target Mode Operation
Figure 3–18. Burst Memory Write Target Transaction with Local-Side Wait State
Note to
(1)
3–70
PCI Compiler User Guide
(1) l_dato[63..32]
This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
(1) l_hdat_ackn
(1) l_beno[7..4]
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_beno[3..0]
lt_tsr[11..0]
(1) ack64n
(1) req64n
cben[3..0]
Figure
lt_framen
(1) par64
ad[31..0]
devseln
lt_dxfrn
framen
lt_ackn
lt_rdyn
stopn
irdyn
trdyn
par
clk
3–18:
1
2
000
Adr
7
3
Figure 3–18
side inserting a wait state. The 64-bit extension signals are not applicable
to the pci_mt32 and pci_t32 functions. The local side deasserts
lt_rdyn in clock cycle 7. The function shows that deasserting lt_rdyn
in clock cycle 7 suspends the local side data transfer in clock cycle 8 by
deasserting lt_dxfrn. Because the local side is unable to accept
additional data in clock cycle 8, the function deasserts trdyn in clock
cycle 8 as well, preventing PCI data from being transferred from the
master device.
Adr-PAR
4
PCI Compiler Version 10.1
D0_L
D0_H
BE0_L
BE0_H
5
shows the same transaction as in
381
D0-H-PAR
D0-L-PAR
6
BE0_H
BE0_L
7
D1_H
BE1_L
BE1_H
D0_H
D1_L
D0_L
8
Adr
781
7
D1-H-PAR
D1-L-PAR
BE2_L
BE1_L
BE1_H
D2_L
D2_H
BE2_H
D1_L
D1_H
9
381
D2-H-PAR
D2-L-PAR
10
BE3_H
BE2_L
BE2_H
D3_H
BE3_L
D2_H
D3_L
D2_L
Figure 3–16
781
11
D3-H-PAR
D3-L-PAR
BE3_L
BE3_H
D3_H
D3_L
12
Altera Corporation
with the local
January 2011
13
000
14
Related parts for IPR-PCI/MT32
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/1
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/4
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCIE/8
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet: