IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 101

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus
Commands
Altera Corporation
January 2011
Table 3–11
responded to by the PCI MegaCore functions.
During the address phase of a transaction, the cben[3..0] bus is used
to indicate the transaction type
The PCI MegaCore functions respond to standard memory read/write,
cache-line memory read/write, I/O read/write, and configuration
read/write commands. The bus commands are discussed in greater detail
in
on page
Notes to
(1)
(2)
(3)
Table 3–11. PCI Bus Command Support Summary
cben[3..0] Value
“Target Mode Operation” on page 3–44
Interrupt acknowledge support can be enabled on the Advanced PCI MegaCore
Function Features page of the Parameterize - PCI Compiler wizard. When
support is enabled, the target accepts the interrupt acknowledge command and
aliases it as a memory read command.
The memory read multiple and memory read line commands are treated as
memory reads. The memory write and invalidate command is treated as a
memory write. The local side sees the exact command on the l_cmdo[3..0] bus
with the encoding shown in
This command is not supported by the pci_mt32 and pci_t32 MegaCore
functions.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
3–88.
Table
PCI Compiler Version 10.1
shows the PCI bus commands that can be initiated or
3–11:
Interrupt acknowledge
Special cycle
I/O read
I/O write
Reserved
Reserved
Memory read
Memory write
Reserved
Reserved
Configuration read
Configuration write
Memory read multiple
Dual address cycle (DAC)
Memory read line
Memory write and invalidate
Bus Command Cycle
Table
(Table
3–11.
(2)
3–11).
(2)
and
(2)
“Master Mode Operation”
Functional Description
No
No
Yes
Yes
Ignored
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Yes
Yes
Yes
Yes
Master
(3)
Yes
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Ignored
Ignored
Yes
Yes
Yes
Yes
Yes
Yes
Target
(1)
(3)
3–27