IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 311

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IPR-PCI/MT32

Manufacturer Part Number
IPR-PCI/MT32
Description
IP CORE Renewal Of IP-PCI/MT32
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCI/MT32

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Figure 7–12. Ordering Logic for PCI-to-Avalon Direction
Altera Corporation
January 2011
Non-Prefetchable
Read/Write
Commands from PCI
From PCI Master
Ctrl
PBA = PCI Bus Access Avalon Slave Port
A2P = Avalon-to-PCI
P2A = PCI-to-Avalon
Data from PCI
Prefetchable
Read/Write Commands
and Write Data from PCI
Prefetchable
Non-
Cmd
Valid
Valid N
Valid 0
Valid 1
Data
Data
Data
PCI Compiler Version 10.1
Data Buffer (FIFO)
P2A Prefetchable
Command/ Write
Command Reg
A2P Pending
A2P Pending
A2P Pending
Read Data N
Read Data 0
Read Data 1
Prefetchable
A2P Non-
(Non-Prefetchable Cmd Valid for a Write
also prevents Prefetchable commands from
being issued to Avalon or Read Data being
sent to the PBA)
Prefetchable
Valid N
Valid 0
Valid 1
Data
Data
Data
Non-
Cmd
Valid
Read/Write Commands
and Write Data to Avalon
Prefetchable Port
Command to Avalon
Non-Prefetchable Port
Functional Description
Read Data to
PBA Port
To PBA Port
To Avalon
Non-Prefetchable
Port
7–43

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