IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 328
IPR-PCI/MT32
Manufacturer Part Number
IPR-PCI/MT32
Description
IP CORE Renewal Of IP-PCI/MT32
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCI/MT32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Control & Status Registers
7–60
PCI Compiler User Guide
31:0
Table 7–28. Avalon Interrupt Enable Register
Bit
One-to-one enable mapping for the
bits in the Avalon-MM interrupt status
register
Avalon Interrupt Enable Register
Name
Avalon-MM Interrupt Enable Register
An Avalon-MM interrupt can be signaled for any of the conditions noted
in the Avalon Interrupt Status Register by setting the corresponding bits
in the Avalon Interrupt Enable Register
PCI interrupts can also be enabled for all of the error conditions in bits
13:8 and 2:0. However, only one of the Avalon-MM or PCI interrupts (not
both) should be enabled for any given bit. There is typically a single
process in either the PCI or Avalon-MM domain that is responsible for
handling the condition reported by the interrupt.
Avalon Mailbox Register Access
A processor local to the interconnect (or any processor not on the PCI bus
attached to the bridge) typically needs write access to a set of
Avalon-to-PCI mailbox registers and read-only access to a set of
PCI-to-Avalon mailbox registers. The specific number (1 or 8) of each of
these types of mailbox registers available is shown in
page
7–5.
PCI Compiler Version 10.1
RW
Access
Mode
When set to 1 indicates the setting of the
associated bit in the Avalon-MM interrupt status
register will cause the Avalon-MM interrupt line
(
Only bits implemented in the Avalon-MM
interrupt status register are implemented in the
enable register. Unimplemented bits cannot be
set to 1.
CraIrq_o
(Table
) to be asserted.
Address 0x3070
Description
7–28).
Table 7–1 on
Altera Corporation
January 2011
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