IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 244

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Compiler with SOPC Builder Flow Design Walkthrough
5–10
PCI Compiler User Guide
Files Generated by SOPC Builder
When SOPC Builder generates your system, it creates a number of new
folders and files in the project directory.
these files.
Figure 5–3. Files Generated By SOPC Builder
PCI Compiler Version 10.1
C:\sopc_pci
chip_top_sim
This folder contains the scripts used to simulate the design in the ModelSim
software.
pci_sim
This folder contains the PCI testbench files.
chip_top.v
This top-level file instantiates all of the modules specified in the SOPC
Builder system.
pci_compiler.vo
This file contains an IP functional simulation model that can be used to
perform functional simulation of the PCI-Avalon bridge variation.
pci_constraints_for_pci_compiler.tcl
This Tcl file needs to be used prior to Quartus II compilation. It contains the
Quartus II constraints that are used to meet the PCI timing requirements.
pci_compiler.log
This file contains information about 1) the fixed translation table that was
defined on the Avalon Configuration page in the PCI Compiler wizard, and
2) the PCI MegaCore function that was instantiated in the PCI-Avalon
bridge.
Other SOPC Builder generated files, including a Verilog HDL file (.v) for
each component in the system and Verilog HDL files for the system
interconnect fabric.
Figure 5–3
describes some of
Altera Corporation
January 2011