IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 225

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Local Reference
Design
Altera Corporation
January 2011
Arbiter (arbiter)
This module simulates the PCI bus arbiter. The module is a two-port
arbiter in which the device connected to port 0 of the arbiter has a higher
priority than the device connected to port 1. For example, if device 0
requests the PCI bus while device 1 is performing a PCI transaction, the
arbiter removes the grant from device 1 and gives it to device 0. This
module allows you to simulate bus parking on devices connected to
port 0 by setting the Park parameter to true. You can change the value of
this parameter in the Altera PCI testbench top-level file.
Pull Up (pull_up)
This module simulates the pull up functionality on the PCI signals. The
ad, cben, framen, irdyn, trdyn, stopn, devseln, perrn, and serrn
signals of the PCI bus are pulled with a weak high value. This action is
necessary to ensure that these signals are never floating or unknown
during your simulation.
The reference design can be used to quickly evaluate Altera PCI
MegaCore functions. This design performs memory read and write
transactions with an LPM_RAM library of parameterized modules (LPM)
function instantiated in the back end. It also performs I/O read and write
transactions with an I/O register that is instantiated locally in the local
master and target blocks. You can replace the reference design with your
application design to verify PCI transactions with other PCI agents.
Figure 4–3
shaded blocks are provided with the PCI testbench.
PCI Compiler Version 10.1
shows the block diagram of the local reference design. The
PCI Compiler User Guide
Testbench
4–15