IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 8

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Contents
Section II. PCI Compiler With SOPC Builder Flow
Chapter 5. Getting Started
Chapter 6. Parameter Settings
viii
PCI Compiler User Guide
Features ................................................................................................................................................... 4–2
PCI Testbench Files ............................................................................................................................... 4–2
Testbench Specifications ....................................................................................................................... 4–6
Local Reference Design ....................................................................................................................... 4–15
Simulation Flow ................................................................................................................................... 4–20
Design Flow ............................................................................................................................................ 5–1
PCI Compiler with SOPC Builder Flow Design Walkthrough ....................................................... 5–2
Simulate the Design ............................................................................................................................. 5–11
Compile the Design ............................................................................................................................. 5–13
Program a Device ................................................................................................................................ 5–14
Upgrading Systems from a Previous Version ................................................................................. 5–15
System Options-1 ................................................................................................................................... 6–1
Value of Multiple Pending Reads ....................................................................................................... 6–6
Master Transactor (mstr_tranx) ...................................................................................................... 4–7
Bus Monitor (monitor) ................................................................................................................... 4–14
Clock Generator (clk_gen) ............................................................................................................ 4–14
Arbiter (arbiter) .............................................................................................................................. 4–15
Pull Up (pull_up) ........................................................................................................................... 4–15
Local Target ..................................................................................................................................... 4–17
DMA Engine ................................................................................................................................... 4–17
Local Master .................................................................................................................................... 4–19
lm_lastn Generator ......................................................................................................................... 4–19
Prefetch ............................................................................................................................................ 4–19
LPM RAM ........................................................................................................................................ 4–19
Create a New Quartus II Project .................................................................................................... 5–3
Set Up the PCI-Avalon Bridge ........................................................................................................ 5–5
Add the Remaining Components to the SOPC Builder System ................................................ 5–7
Complete the Connections in SOPC Builder ................................................................................ 5–8
Generate the SOPC Builder System ............................................................................................... 5–9
Files Generated by SOPC Builder ................................................................................................ 5–10
PROCEDURES and TASKS Sections ........................................................................................ 4–7
INITIALIZATION Section ......................................................................................................... 4–8
USER COMMANDS Section ..................................................................................................... 4–8
Target Transactor (trgt_tranx) ................................................................................................. 4–12
FILE IO section .......................................................................................................................... 4–13
PROCEDURES and TASKS sections ...................................................................................... 4–13
PCI Device Mode ........................................................................................................................ 6–1
PCI Target Performance ............................................................................................................. 6–3
PCI Master Performance ............................................................................................................ 6–5
PCI Compiler Version 10.1
Altera Corporation