IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 95

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
lt_rdyn
lt_framen
lt_ackn
lt_dxfrn
Table 3–7. Target Signals Connecting to the Local Side (Part 2 of 3)
Name
Input
Output
Output
Output
Type
Low
Low
Low
Low
Polarity
PCI Compiler Version 10.1
Local target ready. The local side asserts
a valid data input during target read, or ready to accept data
input during a target write. During a target read,
deassertion suspends the current transfer (i.e., a wait state is
inserted by the local side). During a target write, an inactive
lt_rdyn
wait states on the PCI bus. The only time the function inserts
wait states during a burst is when
on the local side.
lt_rdyn
transferred on the local side. During target write transactions,
lt_rdyn
ample time to issue a retry for the write cycle, the PCI
MegaCore function does not assert
phase unless the local side asserts
local side asserts
complete at least one data phase and it is not going to issue a
retry.
Refer to the
Transactions” on page 3–88
about the
Local target frame request. The
asserted while the PCI MegaCore function is requesting
access to the local side. It is asserted one clock cycle before
the function asserts
data phase of the transaction is transferred to/from the local
side.
Local target acknowledge. The PCI function asserts
to indicate valid data output during a target write, or ready to
accept data during a target read. During a target read, an
inactive
accept data and local logic should delay the bursting operation.
During a target write,
current transfer (i.e., a wait state is inserted by the PCI master).
The
PCI bus master inserts wait states.
Local target data transfer. The PCI MegaCore function asserts
the
successful during a target transaction.
lt_dxfrn
lt_ackn
lt_ackn
lt_rdyn
signal directs the PCI MegaCore function to insert
is sampled one clock cycle before actual data is
has also special functionality. To allow the local side
“Additional Design Guidelines for Target
signal is only inactive during a burst when the
signal when a data transfer on the local side is
lt_rdyn
indicates that the function is not ready to
devseln
functionality.
lt_ackn
Description
section for additional information
to indicate that it intends to
, and it is released after the last
lt_framen
de-assertion suspends the
lt_rdyn
lt_rdyn
trdyn
Functional Description
lt_rdyn
inserts wait states
in the first data
. In this case, the
output is
lt_rdyn
to indicate
lt_ackn
3–21