IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 195

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
64-Bit Single Cycle Memory Write Master Transactions
This section is only applicable to the pci_mt64 MegaCore function. The
pci_mt64 MegaCore function performs 64-bit single-cycle master write
transactions if the Assume ack64n Response option is turned on. (This
option is located on the Advanced PCI MegaCore Function Features
page of the Parameterize - PCI Compiler wizard.) This option can be
used if both of the following statements are true for your system:
■
■
When you turn on the Assume ack64n Response option, the pci_mt64
master can do the following:
■
■
During 64-bit master write transactions in standard operation mode, the
pci_mt64 function waits until the target asserts devseln before
asserting irdyn. This action allows the master to ensure that the correct
number of DWORDs are transferred if a 32-bit target claims the transaction.
Standard operation prevents the pci_mt64 MegaCore function from
supporting 64-bit single-cycle master memory write transactions. When
the pci_mt64 master initiates a single-cycle 64-bit write and the target is
a 32-bit device, the upper 32-bits of data are not transferred across the PCI
bus and are lost from the local side master application. If you turn on the
Assume ack64n Response option, the pci_mt64 MegaCore function can
support 64-bit single-cycle master write transactions because the target is
guaranteed to be a 64-bit device.
single-cycle memory write master transaction where the pci_mt64
function is the master.
The bit width of all devices is known, such as in an embedded system
All 64-bit master transactions are claimed by 64-bit targets that
respond with ack64n asserted
Perform 64-bit single-cycle master write transactions
Initiate 64-bit master write transactions with less initial irdyn
latency
PCI Compiler Version 10.1
Figure 3–44
shows an example of a 64-bit
Functional Description
3–121