IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 86

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–12
PCI Compiler User Guide
ad[63..0]
cben[7..0]
par
par64
idsel
framen
Table 3–2. PCI Interface Signals (Part 2 of 4)
Name
(1)
Tri-State
Tri-State
Tri-State
Tri-State
Input
STS
Type
–
–
–
–
High
Low
Polarity
PCI Compiler Version 10.1
Address/data bus. The
address/data bus; each bus transaction consists of an address
phase followed by one or more data phases. The data phases
occur when
of a 32-bit data phase, only the
data. For
implemented.
Command/byte enable. The
multiplexed command/byte enable bus. During the address
phase, this bus indicates the command. During the data phase,
this bus indicates byte enables. For
only
Parity. The
significant address/data bits and four least significant
command/byte enable bits, i.e., the number of 1s on
ad[31..0]
The
phase. For data phases,
irdyn
a read transaction. Once
clock cycle after the current data phase.
Parity 64. The
significant address/data bits and the four most significant
command/byte enable bits, i.e., the number of 1s on
ad[63..32]
number. The
address phase where
par64
on a write transaction or
transaction. This signal is not implemented in the
and
Initialization device select. The
configuration transactions.
Frame. The
master that indicates the beginning and duration of a bus
operation. When
command signals are present on the
cben[7..0]
32-bit functions). The
the data operation and is deasserted to identify the end of a
transaction.
pci_t32
par
cben[3..0]
asserted on a write transaction or trdyn is asserted on
is valid one clock cycle after either
signal is valid one clock cycle after each address
pci_mt32
par
irdyn
framen
,
par64
cben[3..0]
,
par64
buses (
functions.
cben[7..4]
signal is even parity across the 32 least
framen
is implemented.
and
signal is valid one clock cycle after the
signal is an output from the current bus
and
framen
req64n
ad[31..0]
signal is even parity across the 32 most
ad[63..0]
par
trdyn
trdyn
par
Description
pci_t32
is initially asserted, the address and
cben[7..0]
, and
is valid one clock cycle after either
is valid, it remains valid until one
, and
idsel
signal remains asserted during
is asserted. For data phases,
ad[31..0]
are both asserted. In the case
is asserted on a read
par
pci_mt32
par64
and
, only
bus is a time-multiplexed
ad[63..0]
input is a chip select for
equal an even number.
cben[3..0]
ad[31..0]
irdyn
Altera Corporation
bus is a time-
equal an even
bus holds valid
and
January 2011
pci_mt32
is asserted
and
pci_t32
only for
is
,