IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 136

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–14. Configuration Read Transaction
3–62
PCI Compiler User Guide
lt_tsr[11..0]
cben[3..0]
ad[31..0]
devseln
framen
stopn
trdyn
irdyn
idsel
par
clk
1
2
Configuration Read Transactions
Configuration read transactions are 32 bits. Configuration cycles are
automatically handled by the PCI MegaCore functions and do not require
local side actions.
transaction. This figure applies to all PCI MegaCore functions. The
configuration read transaction is similar to 32-bit single-cycle
transactions, except for the following terms:
■
■
The second case above results in trdyn being asserted in clock cycle 6
instead of clock cycle 7 as shown in
cycle ends in clock cycle 8.
1
000
Adr
A
During the address phase, idsel must be asserted
Because the configuration read does not require data from the local
side, the PCI MegaCore functions assert trdyn independent from
the lt_rdyn signal
3
The local side cannot retry, disconnect, or abort configuration
cycles.
PCI Compiler Version 10.1
Adr-PAR
4
Figure 3–14
Z
Z
BE0_L
5
shows a typical configuration read
100
Figure
6
D0_L
3–14. The configuration read
7
D0-L-PAR
500
Altera Corporation
8
January 2011
000