IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 186

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–112
PCI Compiler User Guide
6
7
8
Table 3–39. Zero-Wait State Burst Memory Write Master Transaction (Part 2 of 3)
Clock
Cycle
The PCI MegaCore function begins the 64-bit memory write transaction with the address phase by
asserting
At the same time, the local side must provide the byte enables for the transaction on the
bus. You can change the byte enables for the successive data words in burst transactions by turning
on Allow Variable Byte Enable During Burst Transactions option in the Advanced PCI
MegaCore Function Features page of the Parameterize - PCI Compiler wizard. Refer to
Variable Byte Enables During Burst Transactions” on page 2–5
opti
The PCI MegaCore function asserts
data. Because
cycle, the PCI MegaCore function asserts
l_hdat_ackn
data word from the
The function asserts
If the arbiter deasserts
lm_tsr[2]
arbiter deasserts
for more information.
The target claims the transaction by asserting
address decode. The target also asserts
data. The target also asserts
During this clock cycle, the function also asserts
phase mode. The function deasserts
local side data transfer during the previous clock cycle but no data was transferred on the PCI side.
To ensure that the proper data is transferred on the PCI bus, the function asserts
first data phase only after the PCI target asserts
The function asserts
irdyn
of clock cycle 9.
The PCI MegaCore function asserts
transfer 64-bit data. The function also asserts
ready to accept data. Because
asserted in the current cycle, the function asserts
l_ldat_ackn
data word from the
on.
and
framen
trdyn
in this clock cycle. For recommendations of how to accommodate scenarios where the
lm_rdyn
, and
signals indicate to the local side that the PCI MegaCore function has transferred one
gntn
and
l_adi
l_adi
are asserted, the first 64-bit data is transferred to the PCI side on the rising edge
lm_tsr[2]
irdyn
l_hdat_ackn
gntn
req64n
in less than three clock cycles, refer to
was asserted in the previous cycle and
bus.
bus.
to inform the target that the function is ready to send data. Because the
in less than 3 clock cycles, the PCI MegaCore function does not assert
trdyn
PCI Compiler Version 10.1
lm_rdyn
.
to indicate to the local side that the PCI bus is in its address phase.
lm_ackn
lm_tsr[9
lm_ackn
to inform the function that it is ready to receive data.
signals indicates to the local side that it has transferred one
ack64n
was asserted in the previous cycle and
lm_dxfrn
lm_ackn
devseln
Event
to indicate to the local side that it is ready to transfer
because its internal pipeline has valid data from the
lm_tsr[3]
] to indicate to the local side that the target can
devseln
lm_dxfrn
to inform the function that it can transfer 64-bit
. The assertion of the
. In this case, the target performs a fast
to inform the local side that the PCI side is
.
to inform the local side that it is in data
“Design Consideration” on page 3–92
. The assertion of the
for more information about this
lm_ackn
is asserted in the current
lm_dxfrn
Altera Corporation
irdyn
lm_ackn
lm_dxfrn
January 2011
and
l_cbeni
during the
“Allow
is
,