IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 208

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

64-Bit Addressing, Dual Address Cycle (DAC)
3–134
PCI Compiler User Guide
Master Mode Operation
A master operation begins when the local-side master interface asserts
the lm_req64n signal to request a 64-bit transaction or the lm_req32n
signal to request a 32-bit transaction. The pci_mt64 function outputs the
reqn signal to the PCI bus arbiter to request bus ownership. The
pci_mt64 function also outputs the lm_adr_ackn signal to the local
side to acknowledge the request. When the lm_adr_ackn signal is
asserted, the local side provides the PCI address on the l_adi[63..0]
bus, the DAC command on l_cbeni[3..0], and the transaction
command on l_cbeni[7..4]. When the PCI bus arbiter grants the bus
to the pci_mt64 function by asserting gntn, pci_mt64 begins the
transaction with a dual address phase. The pci_mt64 function asserts
the framen signal in the first clock cycle, which is called the first address
phase. During the first address phase, the pci_mt64 function drives the
64-bit transaction address on ad[63..0], the dual address cycle
command on cben[3..0], and the transaction command on
cben[7..4]. On the following clock cycle, during the second address
phase, the pci_mt64 function drives the upper 32-bit transaction
address on both ad[63..32] and ad[31..0], and the transaction
command on both cben[7..4] and cben[3..0].
64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction
Figure 3–49
burst memory read transaction.
Figure
in the previous paragraph).
1
3–31, except that
All 32-bit addressing transactions described in
Operation” on page 3–134
transactions, except for the differences described in the previous
paragraph.
PCI Compiler Version 10.1
shows the waveform for a 64-bit address, 64-bit data master
Figure 3–49
Figure 3–49
has two address phases (as described
are applicable for 64-bit addressing
is exactly the same as
Altera Corporation
“Master Mode
January 2011