IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 67

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
HARDWIRE_BARn
HARDWIRE_EXP_ROM
Table 2–1. PCI MegaCore Function Parameters (Part 3 of 5)
Name
Hexadecimal
Hexadecimal
Format
PCI Compiler Version 10.1
H"FF000000"
H"FF000000"
Default Value
Hardwire base address register. n
corresponds to the base address register
number and can be from 0 to 5.
HARDWIRE_BARn is a 32-bit hexadecimal
value that permanently sets the value stored
in the corresponding BAR. This parameter
is ignored if the corresponding
HARDWIRE_BARn_ENA bit is not set to 1.
When the corresponding
HARDWIRE_BARn_ENA bits are set to 1, the
function returns the value in
HARDWIRE_BARn during a configuration
read. To detect a base address register hit,
the function compares the incoming
address to the upper bits of the
HARDWIRE_BARn parameter. The
corresponding BARn parameter is still used
to define the programmable setting of the
individual BAR such as address space type
and number of decoded bits.
Hardwire expansion ROM BAR.
HARDWIRE_EXP_ROM is the default
expansion ROM base address. This
parameter is ignored when
HARDWIRE_EXP_ROM_ENA is set to 0.
When HARDWIRE_EXP_ROM_ENA is set to
1, the function returns the value in
HARDWIRE_EXP_ROM during a
configuration read. To detect base address
hits for the expansion ROM, the functions
compare the input address to the upper bits
of HARDWIRE_EXP_ROM.
HARDWIRE_EXP_ROM_ENA must be set to
enable expansion ROM support, and the
HARDWIRE_EXP_ROM parameter setting
defines the number of decoded bits.
Description
Parameter Settings
2–9