PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 146

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

5.2.6.2
Remote alarm (yellow alarm) is indicated by the periodical pattern "1111 1111 0000 0000
…" in the DL-bits (T1 mode, RC0.SJR = 0). Remote alarm is declared even in the
presence of a bit error rate of up to 10
no longer is detected.
Depending on bit RC0.SJR = 1 the FALC56 generates and detects the remote alarm
according to JT G. 704. In the DL-bit position 16 continuous "1" are transmitted if
FMR0.SRAF = 0 and FMR4.XRA = 1.
5.2.6.3
Generation and checking of CRC6 bits transmitted/received in the E(6:1) bit positions is
done according to ITU-T G.706. The CRC6 checking algorithm is enabled by bit
FMR1.CRC. If not enabled, all check bits in the transmit direction are set. In the
synchronous state received CRC6 errors are accumulated in a 16 bit error counter and
are additionally indicated by an interrupt status.
• CRC6 inversion
If enabled by bit RC0.CRCI, all CRC bits of one outgoing extended multiframe are
automatically inverted in case a CRC error is flagged for the previous received
multiframe. Setting the bit RC0.XCRCI inverts the CRC bits before transmitted to the
distant end. This function is logically ored with RC0.CRCI.
• CRC6 generation/checking according to JT G.706
Setting of RC0.SJR the FALC56 generates and checks the CRC6 bits according to
JT G.706. The CRC6 checksum is calculated including the FS/DL-bits. In synchronous
state CRC6 errors increment an error counter.
5.2.7
The 72-multiframe is an alternate use of the FS-bit pattern and is used for carrying data
link information. This is done by stealing some of redundant multiframing bits after the
transmission of the 12-bit framing header (refer to
of A and B signaling channels (robbed bit signaling) is defined by zero-to-one and one-
to-zero transitions of the FS-bits and is continued when the FS-bits are replaced by the
data link bits.
Data Sheet
framing pattern the FALC56 stays in the asynchronous state, searching for a possible
available framing pattern. This procedure is repeated until the framer has locked on
the right pattern. This automatic synchronization mode has been added in order to
reduce the microprocessor load.
Remote Alarm (yellow alarm) Generation/Detection
CRC6 Generation and Checking (T1/J1)
72-Frame Multiframe (SLC96 Format, T1/J1)
-3
. The alarm is reset when the yellow alarm pattern
146
Figure 36
Functional Description T1/J1
on page 148). The position
FALC56 V1.2
PEB 2256
2002-08-27