PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 42
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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- Download datasheet (6Mb)
Table 4
Pin
No.
67
68
69
70
Data Sheet
Ball
No.
D6
A6
B5
D5
Pin Definitions - System Interface (cont’d)
Symbol
RPA
RPB
RPC
RPD
Input (I)
Output (O)
Supply (S)
O
O
O
Function
Receive Signaling Marker (RSIGM)
PC(1:4).RPC(2:0) = 011
E1: Marks the time slots which are defined by
register RTR(4:1) of every received frame on
port RDO.
T1/J1: Marks the time slots which are defined
by register RTR(4:1) of every received frame
on port RDO, if CAS-BR is not used.
When using the CAS-BR signaling scheme,
the robbed bit of each channel every sixth
frames is marked, if CAS-BR is enabled by
XC0.BRM = 1.
Receive Signaling Data (RSIG)
PC(1:4).RPC(2:0) = 100
The received CAS signaling data is sourced by
this pin. Time slots on RSIG correlate directly
to the time slot assignment on RDO.
Data Link Bit Receive (DLR)
PC(1:4).RPC(2:0) = 101
E1: Marks the S
stream on RDO. The S
time slot 0 of every frame not containing the
frame alignment signal are selected by register
XC0.
T1/J1: Marks the DL-bit position within the data
stream on RDO .
42
a
(8:4)-bits within the data
a
(8:4)-bit positions in
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27
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