PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 195

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Table 52
Register
SIC1
SIC2,
SIC3
LOOP
FMR4
FMR5
XC0
XC1
RC0
RC1
IDLE
ICB(3:1)
CCB(3:1)
LIM0
LIM1
PCD
PCR
XPM(2:0)
IMR(5:0)
GCR
CMR1
CMR2
GPC1
PC(4:1)
PC5
PC6
Data Sheet
Initial Values after reset and FMR1.PMOD = 1 (T1/J1) (cont’d)
00
Initiated
Value
00
00
00
00
00
00
00
9C
00
9C
00
00
00
00
00
00
40
FF
00
00
00
00
00
00
00
00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H,
H,
H
H
H
H
H
,03
00
00
H
H
H
,7B
H
Meaning
2.048 MHz system clocking rate, receive buffer 2 frames,
transmit buffer bypass, data sampled or transmitted on
the falling edge of SCLKR/X, automatic freeze signaling,
data is active in the first channel phase
loop-backs are disabled.
Remote alarm indication towards remote end is disabled.
LFA condition: 2 out of 4/5/6 framing bits, non-auto-
synchronization mode, F12 multiframing, internal bit
robbing access disabled
The transmit clock slot offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channels” selected).
Normal operation (no clear channel operation).
Slave mode, local loop off,
analog interface selected, remote loop off
pulse count for LOS detection cleared
pulse count for LOS recovery cleared
Transmit pulse mask (transmitter in tristate mode)
All interrupts are disabled
Internal second timer, power on
RCLK output: DPLL clock, DCO-X enabled, DCO-X
internal reference clock
SCLKR selected, SCLKX selected, receive
synchronization pulse sourced by SYPR, transmit
synchronization pulse sourced by SYPX
SEC port input active high
Input function of ports RP(A to D): SYPR,
Input function of ports XP(A to D): SYPX
SCLKR, SCLKX, RCLK configured to inputs,
XMFS active low, CLK1 and CLK2 pin configuration
195
Operational Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27