PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
- Current page: 3 of 490
- Download datasheet (6Mb)
Table of Contents
1
1.1
1.2
1.3
2
2.1
2.2
2.3
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.1.3
3.3.2
3.3.3
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.14.1
4.1.14.2
4.1.14.3
4.1.14.4
4.1.14.5
4.2
4.2.1
Data Sheet
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Logic Symbol
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Diagram P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Diagram P-LBGA-81-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Functional Description E1/T1/J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Functional Description E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receive Path in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Framer Operating Modes (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Master Clocking Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receive Short and Long-Haul Interface . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receive Equalization Network (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Receive Line Attenuation Indication (E1) . . . . . . . . . . . . . . . . . . . . . . . . 61
Receive Clock and Data Recovery (E1) . . . . . . . . . . . . . . . . . . . . . . . . 61
Receive Line Coding (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Receive Line Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Loss-of-Signal Detection (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Receive Jitter Attenuator (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Output Jitter (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Framer/Synchronizer (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Receive Elastic Buffer (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Receive Signaling Controller (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Channel Associated Signaling CAS (E1, serial mode) . . . . . . . . . . . 76
Channel Associated Signaling CAS (E1, µP access mode) . . . . . . . 77
Mixed Byte/Word Access to the FIFOs . . . . . . . . . . . . . . . . . . . . . . . 52
FIFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HDLC or LAPD access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Support of Signaling System #7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Sa-Bit Access (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3
FALC56 V1.2
PEB 2256
2002-08-27
Page
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