PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 236

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XSIF
XS13
XS15
Transmit Control 0 (Read/Write)
Value after reset: 00
XC0
SA(8:4)E
Data Sheet
SA8E
7
Transmit Spare Bit For International Use (FAS Word)
First bit in the FAS word. Only significant in doubleframe format. If not
used, this bit should be fixed to "1". If one of the time slot 0 transparent
modes is enabled (bits XSP.TT0, or TSWM.TSIF), bit XSP.XSIF is
ignored.
Transmit Spare Bit (Frame 13, CRC-Multiframe)
First bit in the service word of frame 13 for international use. Only
significant in CRC-multiframe format. If not used, this bit should be
fixed to "1". The information of XSP.XS13 is shifted into internal
transmission buffer with beginning of the next following transmitted
CRC multiframe.
If automatic transmission of submultiframe status is enabled by bit
XSP.AXS, or, if one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIS is enabled, bit XSP.XS13 is ignored.
Transmit Spare Bit (Frame 15, CRC-Multiframe)
First bit in the service word of frame 15 for international use. Only
significant in CRC-multiframe format. If not used, this bit should be
fixed to "1". The information of XSP.XS15 is shifted into the internal
transmission buffer with beginning of the next following transmitted
CRC multiframe.
If automatic transmission of submultiframe status is enabled by bit
XSP.AXS, or, if one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIF is enabled, bit XSP.XS15 is ignored.
S
0 =
1 =
SA7E
a
H
-Bit Signaling Enable
ignored. If one of the time slot 0 transparent modes XSP.TT0 or
TSWM.TSIS is enabled, bit XSP.AXS has no function.
Standard operation.
Setting this bit makes it possible to send/receive a LAPD
protocol in any combination of the S
outgoing/incoming data stream. The on chip signaling controller
has to be configured in the HDLC/LAPD mode. In transmit
SA6E
SA5E
236
SA4E
XCO10
XCO9
a
-bit positions in the
XCO8
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(22)