PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 413

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

Framer Receive Status Register 1 (Read)
FRS1
EXZD
PDEN
LLBDD
LLBAD
Data Sheet
EXZD
7
Excessive Zeros Detected
Significant
(FMR2.EXZE = 1).
Set after detecting of more than 7 (B8ZS code) or more than 15 (AMI
code) contiguous zeros in the received bit stream. This bit is cleared
on read.
Pulse-Density Violation Detected
The pulse-density of the received data stream is below the
requirement defined by ANSI T1. 403 or more than 14 consecutive
zeros are detected. With the violation of the pulse-density this bit is
set and remains active until the pulse-density requirement is fulfilled
for 23 consecutive "1"-pulses.
Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
Line Loop-Back Deactivation Signal Detected
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 33,16 ms with a bit error rate less
than 10
exceed 10
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes an LLBSC interrupt.
Line Loop-Back Activation Signal Detected/PRBS Status
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM = 0: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 33,16 ms with
a bit error rate less than 10
error rate does not exceed 10
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes an LLBSC interrupt.
PDEN
-2
. The bit remains set as long as the bit error rate does not
-2
.
only
LLBDD
if
413
excessive
LLBAD
-2
. The bit remains set as long as the bit
-2
.
zeros
detection
XLS
T1/J1 Registers
FALC56 V1.2
XLO
0
is
PEB 2256
2002-08-27
enabled
(4D)