PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 191
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Table 47
Operational Set Up
Select framing
Framing additions
Synchronization mode
Signaling mode
Features like channel loop-back, idle channel activation, extensions for signaling
support, alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS,
remote alarm) and control of synchronization in connection with consequent actions to
remote end and internal system depend on the activation procedure selected.
Note: Read access to unused register addresses: value should be ignored.
Specific E1 Register Settings
The following is a suggestion for a basic initialization to meet most of the E1
requirements. Depending on different applications and requirement any other
initialization can be used.
Table 48
FMR0.XC0/
FMR0.RC0/
LIM1.DRS
FMR3.CMI
PCD = 0A
PCR = 15
LIM1.RIL(2:0) = 02
E1 Framer Initialization
The selection of the following modes during the basic initialization supports the ETSI
requirements for E-Bit Access, remote alarm and synchronization (please refer also to
FALC56 driver code of the evaluation system EASY22554 and application notes) and
Data Sheet
Write access to unused register addresses: should be avoided, or set to “00” hex.
All control registers (except XFIFO, XS(16:1), CMDR, DEC) are of type Read/
Write.
H
H
Initialization Parameters (E1) (cont’d)
Line Interface Initialization (E1)
H
The FALC56 supports requirements for the analog line interface
as well as the digital line interface. For the analog line interface
the codes AMI and HDB3 are supported. For the digital line
interface modes (dual- or single-rail) the FALC56 supports AMI,
HDB3, CMI (with and without HDB3 precoding) and NRZ.
LOS detection after 176 consecutive “zeros” (fulfills G.775).
LOS recovery after 22 “ones” in the PCD interval. (fulfills G.775).
LOS threshold of 0.6 V (fulfills G.775).
191
FMR2.RFS(1:0), FMR1.XFS
RC1.ASY4, RC1.SWD
FMR1.AFR, FMR2.ALMF
XSP, XSW, FMR1.ENSA, XSA(8:4),
TSWM, MODE, CCR1, CCR2, RAH(2:1),
RAL(2:1)
Operational Description E1
FALC56 V1.2
PEB 2256
2002-08-27
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