PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 409
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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10.4
Receive FIFO - HDLC Channel 1 (Read)
RFIFO
RFIFO
Reading data from RFIFO can be done in an 8-bit (byte) or 16-bit (word) access
depending on the selected bus interface mode. The LSB is received first from the serial
interface.
The size of the accessible part of RFIFO is determined by programming the bits
CCR1.RFT(1 0) (RFIFO threshold level). It can be reduced from 32 bytes (reset value)
down to 2 bytes (four values: 32, 16, 4, 2 bytes).
Data Transfer
Up to 32 bytes/16 words of received data can be read from the RFIFO following a RPF
or a RME interrupt.
RPF Interrupt: A fixed number of bytes/words to be read (32, 16, 4, 2 bytes). The
message is not yet complete.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
RFIFO is released by issuing the RMC (Receive Message Complete) command.
Receive Buffer Delay (Read)
RBD
RBD(5:0)
Data Sheet
RF15
RF7
Detailed Description of T1/J1 Status Registers
7
7
Receive Elastic Buffer Delay
These bits informs the user about the current delay (in time slots)
through the receive elastic buffer. The delay is updated every 386 or
193 bits (SIC1.RBS(1:0)). Before reading this register the user has to
set bit DEC.DRBD in order to halt the current value of this register.
After reading RBD updating of this register is enabled. Not valid if the
receive buffer is bypassed.
000000 = Delay < 1 time slot
...
111111 = Delay > 63 time slots
RBD5
RBD4
409
RBD3
RBD2
RBD1
T1/J1 Registers
RBD0
FALC56 V1.2
RF0
RF8
0
0
PEB 2256
2002-08-27
(00)
(01)
(49)
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