PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 257
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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RESX
RESR
TTRF
DAF
Data Sheet
Rising Edge Synchronous Pulse Transmit
Depending on this bit all transmit system interface data and marker
are clocked or sampled with the selected active edge.
CMR2.IXSC = 0:
0
1
CMR2.IXSC = 1:
value of RESX bit has no impact on the selected edge of the PCM
highway clock but value of RESR bit is used as RESX.
Example: If RESR = 0, the rising edge of PCM highway clock is the
selected one for sampling data on XDI and vice versa.
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked with the selected active edge.
0 =
1 =
Note: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is
TTR Register Function (Fractional E1 Access)
Setting this bit the function of the TTR(4:1) registers is changed. A
one in each TTR register forces the XSIGM marker high for the
corresponding time slot and controls sampling of the time slots
provided on pin XSIG. XSIG is selected by PC(4:1).XPC(3:0).
Disable Automatic Freeze
0 =
1 =
latched with the first falling edge of the selected PCM highway
clock.
latched with the first rising edge of the selected PCM highway
clock.
Latched with the first falling edge of the selected PCM highway
clock.
Latched with the first rising edge of the selected PCM highway
clock.
inverse (1 = falling edge, 0 = rising edge)
Signaling is automatically frozen if one of the following alarms
occurred: Loss-Of-Signal (FRS0.LOS), Loss of CAS Frame
Alignment (FRS1.TS16LFA), or receive slips (ISR3.RSP/N).
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer
is stopped if SIC2.FFS is set. Significant only if the serial
signaling access is enabled.
257
FALC56 V1.2
E1 Registers
PEB 2256
2002-08-27
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