PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 385

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

XPC(3:0)
Data Sheet
011 = RSIGM: Receive Signaling Marker (Output)
100 = RSIG: Receive Signaling Data (Output)
101 = DLR: Data Link Bit Receive (Output)
110 = FREEZE: Freeze Signaling (Output)
111 = RFSP: Receive Frame Synchronous Pulse (Output)
Transmit multifunction Port Configuration
The multifunction ports XP(A to D) are bidirectional. After Reset these
ports are configured as inputs. With the selection of the pin function
the In/Output configuration is also achieved. Each of the four different
input functions (SYPX, XMFS, XSIG, TCLK) may only be selected
once. No input function must be selected twice or more. SYPX and
XMFS should not be selected in parallel. Register PC1 configures
port XPA, while PC2
XPD.
0000 = SYPX: Synchronous Pulse Transmit (Input)
0001 = XMFS: Transmit Multiframe Synchronization (Input)
0010 = XSIG: Transmit Signaling Data (Input)
Marks the time slots which are defined by register RTR(4:1)
of every frame on port RDO.
The received CAS multiframe is transmitted on this pin. Time
slot on RSIG correlates directly to the time slot assignment on
RDO.
Marks the S
The freeze signaling status is active high by detecting a Loss-
of-signal alarm, or a Loss of CAS Frame Alignment or a
receive slip (positive or negative). It stays high for at least one
complete multiframe after the alarm disappears. Setting
SIC2.FFS enforces a high on pin FREEZE.
Marks the frame begin in the receivers synchronous state.
This marker is active low for 488 ns with a frequency of 8 kHz.
Together with register XC(1:0) SYPX defines the frame begin
on the transmit system interface ports XDI and XSIG.
Together with register XC(1:0) XMFS defines the frame and
multiframe begin on the transmit system interface ports XDI
and XSIG. Depending on PC5.CXMFS the signal on XMFS is
active high or low.
Input for transmit signaling data received from the signaling
highway. Optionally sampling of XSIG data is controlled by
the active high XSIGM marker.
a
-bits within the data stream on RDO.
385
port XPB, PC3
port XPC and PC4
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27
port