PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 156
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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same high frequency clock as the receive jitter attenuator. It synchronizes either to the
working clock of the transmit backplane interface or the clock provided on pin TCLK or
the receive clock RCLK (remote loop/loop-timed). The DCO-X attenuates the incoming
jitter starting at 6 Hz with 20 dB per decade fall-off. With the jitter attenuated clock, which
is directly depending on the phase difference of the incoming clock and the jitter
attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the JATT
buffer (2 frames, remote loop). Wander with a jitter frequency below 6 Hz is passed
transparently.
The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.
The jitter attenuated clock is output on pin XCLK or optionally on pin CLK2.
In case of missing clock on pin SCLKX the DCO-X centers automatically, if selected by
bit CMR2.DCOXC = 1.
The transmit jitter attenuator can be disabled. In that case data is read from the transmit
elastic buffer with the clock sourced on pin TCLK (1.544 or 6.176 MHz). Synchronization
between SCLKX and TCLK has to be done externally.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a
transmit clock which is frequency synchronized on RCLK. In this configuration the
transmit elastic buffer has to be enabled.
Figure 51
Data Sheet
RL1/2
RDIP/N
ROID
XL1/2
XDOP/N
XOID
DRS
Clocking in Remote Loop Configuration (T1/J1)
Equalizer
Driver
Line
Shaper
DPLL
Pulse
DRS
RCLK
156
RCLK
Attenuator
Transmit
Buffer
JATT
Jitter
RCLK
Functional Description T1/J1
Decoder
Encoder
Clock
Line
Line
Unit
FALC56 V1.2
Receive
Data
Transmit
Data
MCLK
ITS10299
PEB 2256
2002-08-27
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