PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 367
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
- Current page: 367 of 490
- Download datasheet (6Mb)
JATT, RL
DRS
Pulse Count Detection Register (Read/Write)
Value after reset: 00
PCD
PCD(7:0)
Data Sheet
PCD7
7
Remote Loop Transmit Jitter Attenuator
00 = Normal operation. The remote loop transmit jitter attenuator is
01 = Remote Loop active without transmit jitter attenuator enabled.
10 = not assigned
11 = Remote Loop and remote loop jitter attenuator active. Received
Note: JATT is only used to define the jitter attenuation during remote
0 =
1 =
Pulse Count Detection
A LOS alarm (red alarm) is detected if the incoming data stream has
no transitions for a programmable number T consecutive pulse
positions. The number T is programmable by the PCD register and
can be calculated as follows:
T = 16
The maximum time is: 256
pulse resets the internal pulse counter. The counter is clocked with
the receive clock RCLK.
Dual-Rail Select
H
disabled. Transmit data bypasses the remote loop jitter
attenuator buffer.
Transmit data bypasses the remote loop jitter attenuator buffer.
data from pins RL1/2 or RDIP/N or ROID is sent "jitter-free" on
ports XL1/2 or XDOP/N or XOID. The de-jittered clock is
generated by the DCO-X circuitry.
The ternary interface is selected. Multifunction ports RL1/2 and
XL1/2 become analog in/outputs.
The digital dual-rail interface is selected. Received data is
latched on multifunction ports RDIP/RDIN while transmit data is
output on pins XDOP/XDON.
loop operation. Jitter attenuation during normal operation is
not affected.
(N+1); with 0
367
N
255.
16
648 ns = 2.65 ms. Every detected
T1/J1 Registers
PCD0
FALC56 V1.2
0
PEB 2256
2002-08-27
(38)
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