PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 433
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Interrupt Status Register 3 (Read)
ISR3
All bits are reset when ISR3 is read.
If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are masked by
register IMR3. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
ES
SEC
LLBSC
Data Sheet
ES
7
Errored Second
This bit is set if at least one enabled interrupt source by ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected
FER = Framing error received
CER = CRC error received
AIS
LOS = Loss-of-signal (red alarm)
CVE = Code violation detected
SLIP = Transmit slip or receive slip positive/negative detected
Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK.
Line Loop-Back Status Change/PRBS Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal is detected over a period of 33,16 ms with a bit error
rate less than 10
The LLBSC bit is also set, if the current detection status is left, i.e., if
the bit error rate exceeds 10
The actual detection status can be read from the FRS1.LLBAD and
FRS1.LLBDD, respectively.
PRBS Status Change
LCR1.EPRM = 1: With any change of state of the PRBS synchronizer
this bit is set. The current status of the PRBS synchronizer is
indicated in FRS1.LLBAD.
SEC
= Alarm indication signal (blue alarm)
-2
.
433
LLBSC
-2
.
RSN
T1/J1 Registers
FALC56 V1.2
RSP
0
PEB 2256
2002-08-27
(6B)
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