PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 317

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

RA16
RSN
RSP
Interrupt Status Register 4 (Read)
ISR4
All bits are reset when ISR4 is read.
If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are masked by
register IMR4. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
XSP
XSN
Data Sheet
XSP
7
Remote Alarm Time Slot 16 Status Change
A change in the remote alarm bit in CAS multiframe alignment word
is detected.
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency
of the receive system interface working clock based on 2.048 MHz. A
frame is skipped. It is set during alarm simulation.
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of
the receive system interface working clock based on 2.048 MHz. A
frame is repeated. It is set during alarm simulation.
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame
is repeated. After a slip has performed writing of register XC1 is not
necessary.
Transmit Slip Negative
The frequency of the transmit clock is greater than the frequency of
the transmit system interface working clock based on 2.048 MHz. A
frame is skipped. After a slip has performed writing of register XC1 is
not necessary.
XSN
RME2
RFS2
317
RDO2
ALLS2
XDU2
RPF2
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(6C)