PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 251

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

SCF
ELT
Loop Code Register 1 (Read/Write)
Value after reset: 00
LCR1
EPRM
XPRBS
Data Sheet
EPRM
7
XPRBS
Select Corner Frequency of DCO-R
Setting this bit reduces the corner frequency of the DCO-R circuit by
the factor of ten to 0.2 Hz.
Note: Reducing the corner frequency of the DCO-R circuitry
increases the synchronization time before the frequencies are
synchronized.
Enable Loop-Timed
0 =
1 =
Enable Pseudo-Random Binary Sequence Monitor
0 =
1 =
Transmit Pseudo-Random Binary Sequence
A one in this bit position enables transmission of a pseudo-random
binary sequence to the remote end. Depending on bit LLBP the PRBS
is generated according to 2
restriction (ITU-T O. 151).
H
Normal operation
Transmit clock is generated from the clock supplied by MCLK
which is synchronized to the extracted receive route clock. In
this configuration the transmit elastic buffer has to be enabled.
Refer to register XSW.XTM. For correct operation of loop timed
the remote loop (bit LIM1.RL = 0) must be inactive and bit
CMR1.DXSS must be cleared.
Pseudo-Random Binary Sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the
CEC2 error counter with each detected PRBS bit error. With
any change of state of the PRBS internal synchronization
status an interrupt ISR1.LLBSC is generated. The current
status of the PRBS synchronizer is indicated by bit
RSP.LLBAD.
LDC1
LDC0
251
LAC1
15
-1 or 2
LAC0
20
-1 with a maximum-14-zero
FLLB
LLBP
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(3B)