PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 380
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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IRSP
IRSC
IXSP
IXSC
Data Sheet
Internal Receive System Frame Sync Pulse
0 =
1 =
Internal Receive System Clock
0 =
1 =
Internal Transmit System Frame Sync Pulse
0 =
1 =
Internal Transmit System Clock
0 =
1 =
The frame sync pulse for the receive system interface is
sourced by SYPR (if SYPR is applied). If SYPR is not applied,
the frame sync pulse is derived from RDO output signal
internally free running).
The use of IRSP = 0 is recommended.
The frame sync pulse for the receive system interface is
internally sourced by the DCO-R circuitry. This internally
generated frame sync signal can be output (active low) on
multifunction ports RP(A to D) (RPC(2:0) = 001
Note: This is the only exception where the use of RFM and
SYPR is allowed at the same time. Because only one set of
offset registers (RC1/0) is available, programming is done by
using the SYPR calculation formula in the same way as for the
external SYPR pulse. Bit IRSC must be set for correct
operation.
The working clock for the receive system interface is sourced
by SCLKR of or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
The working clock for the receive system interface is sourced
internally by DCO-R or in bypass mode by the extracted receive
clock. SCLKR is ignored.
The frame sync pulse for the transmit system interface is
sourced by SYPX.
The frame sync pulse for the transmit system interface is
internally sourced by the DCO-R circuitry. Additionally, the
external XMFS signal defines the transmit multiframe begin.
XMFS is enabled or disabled by the multifunction port
configuration. For correct operation bits CMR2.IXSC/IRSC
must be set. SYPX is ignored.
The working clock for the transmit system interface is sourced
by SCLKX.
The working clock for the transmit system interface is sourced
internally by the working clock of the receive system interface.
SCLKX is ignored.
380
T1/J1 Registers
FALC56 V1.2
B
).
PEB 2256
2002-08-27
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