PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 339

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

EITS
ITF
XMFA
Data Sheet
Enable Internal Time Slot 0 to 31 Signaling - HDLC Channel 1
0 =
1 =
Interframe Time Fill - HDLC Channel 1
Determines the idle (= no data to be sent) state of the transmit data
coming from the signaling controller.
0
1
Transmit Multiframe Aligned - HDLC Channel 1
Determines the synchronization between the framer and the
corresponding signaling controller.
0 =
1 =
Note: During the transmission of the XFIFO content, the SYPX or
Continuous logical 1 is output
Continuous flag sequences are output (01111110 bit patterns)
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is disabled.
Internal signaling in time slots 0 to 31 defined by registers
RTR(4:1) or TTR(4:1) is enabled.
The contents of the XFIFO is transmitted without multiframe
alignment.
The contents of the XFIFO is transmitted multiframe aligned.
If CCR1.EDLXis set, transmission of DL-bits is started in F72
format with frame 26. The first byte in XFIFO is transmitted in
the first time slot selected by TTR(4:1) and so on.
After receiving a complete multiframe in the time slot mode
(RTR(4:1)) an ISR0.RME interrupt is generated, if no HDLC or
BOM mode is enabled. In DL-bit access (CCR1.EDLX/
EITS = 10) XMFA is not valid.
XMFS interval time should not be changed, otherwise the
XFIFO data has to be retransmitted.
339
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27